In a metal-oxide semiconductor field-effect transistor (MOSFET), a thin dielectric barrier is used to isolate the gate and the channel. The voltage applied to the gate induces an electric field across the dielectric barrier to control the free-carrier concentration in the channel region. Such devices are referred to as insulated-gate field-effect transistors (IGFETs), or simply as MOS transistors. A. Grebene, Bipolar and MOS Analog Integrated Circuit Design (1984 J. Wiley & Sons) 106. It should be noted that the term MOS applies even though the gate may be a non-metallic conductor, such as a highly doped polysilicon.
MOS transistors are classified as P-channel or N-channel devices, depending on the conductivity type of the channel region. In addition, they can also be classified as “enhancement” or “depletion” devices. In a depletion-type MOSFET, a conducting channel exists under the gate when no gate voltage is applied. The applied gate voltage controls the current flow between the source and the drain by depleting a part of this channel. In an enhancement-type MOS transistor, no conductive channel exists between the source and the drain at zero applied drain voltage. As a gate bias of proper polarity is applied and increased beyond a threshold value VT, a localized inversion layer is formed directly below the gate. This inversion layer serves as a conducting channel between the source and the drain electrodes. If the gate bias is increased further, the resistivity of the induced channel is reduced, and the current conduction from the source to the drain is enhanced. Id at 106-107.
MOS transistors make good switches because (1) when the device is ON and conducting, there is no inherent dc offset voltage between the source and drain, and (2) the control terminal (the gate) is electrically isolated from the signal path, thus no dc current flows between the control path and the signal path. Id at 303.
Normally, all the active regions of the MOSFET are reverse-biased with respect to the substrate. Thus, adjacent devices fabricated on the same substrate are electrically isolated without requiring separate isolation diffusions. The bulk of the semiconductor region is normally inactive since the current flow is confined to a thin surface channel directly below the gate. The bulk of the MOS transistor is called the “body” or “back gate” and, for efficient operation, is normally tied to the same potential as the source. Id at 108. In certain circuits, such as the conventional voltage level shifting circuits discussed below, however, it may be necessary to apply a different potential to the body in order to maintain the source-body junction in reverse biased condition and prevent a large junction current from flowing inside the transistor. Such current will interfere with normal circuit operation and can permanently damage the device or circuit.
Thus, for an N-channel MOS (NMOS) transistor the body (or bulk) must be biased to make it negative with respect to both source and drain, and for a P-channel MOS (PMOS) transistor the body must be biased to make it positive with respect to both source and drain. In a depletion device, if the reverse voltage VSB=VS−VB between the body and the source (and hence the channel) is increased, the depletion region around the channel will become wider. This will increase the minimum gate voltage VG=VT necessary to maintain the depletion region without creating a conductive channel. In an enhancement device, on the other hand, increasing the reverse voltage will narrow the enhancement region, raising the voltage VG=VT needed to develop the enhancement region to create the channel. This dependence of VT on the magnitude of the reverse biasing voltage VSB is known as the “body effect.” In addition to increasing the magnitude of the threshold VT, another undesired result of the body effect is to reduce the device transconductance and the output impedance when the device is operated in a cascode configuration. The body effect phenomenon is a major limitation of MOS devices operated at VS≠VB. See, Id at 268-271; and R. Gregorian, et al., Analog MOS Integrated Circuits for Signal Processing (1986 J. Wiley & Sons) 77-78.
FIG. 1A illustrates a typical MOS transistor with its substrate body tied to its source potential. Such arrangement, shown for a PMOS transistor in FIG. 1A, is equivalent to a PN diode connection between a drain and source, as shown in FIG. 1B. A VB=VSconnection is usually effective to reverse-bias the PN junction and, because it minimizes the threshold voltage VT, results in efficient operation and minimum area requirements (viz. channel length and width) for the device. Also, such connections provide relatively uniform resistivity for variations in applied voltage V+ in multiple MOS transistor layouts. Body-to-source reverse biasing will not, however, work for circuits wherein the MOS device will be subjected to varying voltages, sometimes placing the drain voltage VD at a forward biasing potential relative to the source. This is so for a circuit wherein distinct MOS switches are connected in parallel to drive a capacitive load with a selected one of a number of different voltages. An example of such a driver arrangement exists in a matrix-addressable flat-panel display column driver, in which different MOS transistors are used to apply a selected one of different voltages to a display column, such as for gray scale control of imaging pixels. In such a voltage level shifter arrangement, the requirement for maintaining a reverse bias across the body diode junction prevents tying the body to the source. This is because any voltage applied to the capacitive load, except the lowest one, will forward bias the other body diodes, preventing charge of the load.
This limitation can be seen by examination of the operation of a conventional voltage level shifting circuit shown of FIG. 2, wherein a plurality of PMOS transistors M1, M2, M3 are connected in parallel, for respectively driving a capacitive load CL with a selected different voltage level V1 (e.g., 5 volts), V2 (e.g., 10 volts), or V3 (e.g., 20 volts). If a control voltage VG≧VT is applied to place transistor M1 in the ON condition (with transistor M2, M3 in the OFF condition), voltage V1 (5 volts) will be applied across the load CL and also to the drains of transistors M2, M3. Because the sources of transistors M2, M3 are at higher potentials, this does not pose a forward biasing problem for the PN junctions of M2, M3. The voltage differential VDS for M2 would be V1−V2=−5 volts; and for M3 would be V1−V3=−15 volts. So, even with VBS=0, the body diodes of M2, M3 would be reverse biased, and the voltage V1 would be applied to charge the load CL. This would not be the case, however, if one of the transistors M2 or M3 were placed in the ON condition. If transistor M2 were ON (with transistors M1, M3 OFF), the V2 (10 volts) would be applied to the drains of M1, M3. This would leave M3 with a reverse biased body diode (VDSS=V2−V1=−10 volts), but would forward bias the body diode of M1 (VDS1=V2−V1=5 volts). Thus, current would flow in the body of M1 for the M1 OFF condition, preventing charge-up of load CL. For M3 in the ON condition (with M1 and M2 OFF), both M1 and M2 would have forward biased body diodes and current flowing through their bodies would prevent charge-up of load CL.
To overcome this problem, the bodies or “back gates” of transistors M1, M2 connected to lower voltages V1, V2 are connected to a voltage VB≧VS in order to maintain the reverse biased condition. The greater source-to-body bias VSB will, however, increase the body effect for the transistors M1, M2 connected to apply the lower voltages V1, V2, and the gain of those devices will be decreased. Thus, because the channel-ON resistance RDSON directly correlates to the gain, in order to achieve the same target RDSON, the MOS structures M1, M2 with the larger body effects will require more area or “footprint”. So, all MOS switches except the one tied to the largest voltage, must be made larger to accommodate the larger higher voltage differentials. Higher potential difference between the body and the source will also dramatically reduce the efficiency of the operation of the device. Moreover, uniformity of the respective resistances RDSON between the different devices will be reduced, giving less control over the saturation current point, with the risk of putting the power supply under greater burden due to transients.
It is, therefore, an object of the present invention to overcome the forward biasing problem in voltage level shifters and other circuits which subject MOS devices to different voltage levels, without the need to use larger MOS transistors to compensate for the body effect.